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SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. As the titles indicate, each book covers a different sphere of SystemVerilog; the former on the design modeling constructs and the latter on the design verification constructs.
On purpose. The book shows common coding mistakes that the authors or others have made in their Verilog or SystemVerilog code. Often these mistakes looked like perfectly reasonable code, but cause functional errors in simulation or synthesis that were difficult to debug.
And that's the definition of a Gotcha -- code that looks correct, but which behaves differently than expected.
The examples in this book are not available for download, but they are very short and easy to type in. This book examines the synthesizable portion of those extensions, which are extensive and important for RTL designers to take advantage of. This book does not cover the full, traditional Verilog HDL -- this book for engineers who already know Verilog, and need to understand what SystemVerilog adds to Verilog, specific for modeling at the RTL level.